Emulator custom chips have a need to exchange data at relatively high data rates, even though the chips may be separated from each other by relatively long distances, such as beyond tens of centimeters. A major hurdle to overcome in any such chip-to-chip communication link is synchronization. Clock signals are typically used to provide some measure of synchronization. Signals are sent and received in synchronicity with a clock. Clocks may be global or local. A global board-level clock is distributed to a plurality of chips, however due to propagation delays it may arrive at each chip at slightly different times. This is called clock skew. Local clocks are generated by the chips themselves (although they may be derived from external signaling such as a global clock). However, local clocks also suffer from the skew problem between chips. Even if chip-to-chip data transfer is source-synchronous, problems of synchronization can occur at the receiver flip-flop due to different parameters such as jitter/noise at the chip or board level, skew between the emitter and receiver clocks, propagation delay between the emitter chip and the receiver chip.
When data is received that is not synchronized with the clock that the receiver is using, data can be distorted or even lost. Various approaches have been taken to resolve the inter-chip synchronicity problem. In one approach, the clock is adjusted to match the timing of the incoming data. In particular, incoming data from another chip is oversampled by four different receiver clocks. The clock that works best is used. In general, some of the previous approaches have required a relatively large amount of power and area on an integrated circuit chip, and are unable to sufficiently correct for unexpected latencies between chips.
Improved systems are needed for establishing and/or maintaining synchronization between integrated circuit chips. Such a need is particularly felt in the field of circuit design emulation, where a single synchronized operation may be performed between different chips in phase with a specific clock cycle. Such improved systems should preferably be able to perform such synchronization despite unexpected latencies that occur in the data paths between chips.